`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/10 17:30:25
// Design Name: 
// Module Name: Add_4bit_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Add_4bit_tb(
    );
    
    reg[3:0] A_tb, B_tb;
    reg CI_tb;
    wire[4:0] Y_tb;
    
    integer a,b;
    initial
    begin
        for (a = 0; a < 16; a = a + 1)
        begin
            for (b = 0; b < 16; b = b + 1)
            begin
                A_tb = a;
                B_tb = b;
                CI_tb = 0;
                #100;
                CI_tb = 1;
                #100;
            end 
        end
    end
    
    Add_4bit_TOP add_4bit_TOP_tb(
        .A(A_tb),
        .B(B_tb),
        .CCI(CI_tb),
        .Y(Y_tb)
    );
    
endmodule
